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Choosing a long source/drain extension length (LSDE) maybe effectively reduces the leakage between source/gate and drain/gate, but the S/D series resistance is increased and the drive current in p-channel FinFETs is suffered. Of course, the DIBL effect can be controlled well in device model and the channel punch-through effect also can be suppressed to decrease the standby current in ICs. Balancing...
Localization abstraction is a powerful technique that has long been a solution to the scalability problem of hardware model checking. However, computation resources are often inefficiently consumed during the repeated trial-and-errors between abstraction refinement engines and proof engines. To this end, many efforts have been made to combine the two independent techniques for better efficiency in...
Quasi-Delay insensitive (QDI) circuits are the most robust and practical that can be built and are resilient to process, temperature and voltage (PVT) variations. Although there are many research papers that can translate synchronous designs into asynchronous sequential designs, to the best of our knowledge, there is neither QDI finite state machine (FSM) models proposed nor algorithms or tools designed...
For a design with multiple functional errors, multiple patches are usually needed to correct the design. Previous works on logic rectification are limited to either single-fix or partial-fix rectifications. In other words, only one or part of the erroneous behaviors can be fixed in one iteration. As a result, it may lead to unnecessarily large patches or even failure in rectification. In this paper,...
ECO re-mapping is a key step in functional ECO tools. It implements a given patch function on a layout database with a limited spare cell resource. Previous ECO re-mapping algorithms are based on existing technology mappers. However, these mappers are not designed to consider the resource limitation and thus the corresponding ECO results are generally not good enough, or even become much worse when...
Dynamic power saving is gaining its dominance in modern low power designs, while clock gating, which blocks unnecessary clock switching activities, is one of the most efficient approaches to reduce the dynamic power. In this paper, we exploit the interpolation technique in a SAT-based clock gating algorithm in order to grant a greater flexibility in enlarging the gating capabilities over the original...
To cope with last-minute design bugs and specification changes, engineering change order (ECO) is usually performed toward the end of the design process. This paper proposes an automatic ECO synthesis algorithm by interpolation. In particular, we tackle the problem by a series of partial rectifications. At each step, partial rectification can reduce the functional difference between an old implementation...
Functional rectification in late design stages has been a crucial process in modern complex system design. This paper proposes a robust functional ECO engine, which applies SAT proof minimization and interpolation techniques to automate patch construction to make old implementation and golden specification functionally equivalent. The SAT proof minimization technique provides a sound and efficient...
In this paper, we proposed an automatic target constraint generation (ATCG) technique to automatically generate compact and high-quality constraints for the guided random simulation environment. Our objective is to tackle the biggest bottleneck of the entire constrained random simulation process - the time-consuming and error-prone manual testbench composition process. By taking only the design under...
In this paper, we proposed a novel interpolant generation algorithm without constructing the resolution graph of the unsatisfiability proof. Our algorithm generates the interpolant by building sub-interpolants from conflict analyses and then merges them based on the last decision conflict. The experimental results show that our algorithm has the advantages over the prior interpolant generation techniques...
Timing closure has always been the biggest bottleneck in the modern VLSI design flow. Traditional timing verification techniques such as static timing analysis (STA) are usually too conservative or sometimes too optimistic. This inaccuracy may lead to an unnecessary procrastination of time to market or even silicon failure. It is mainly due to the inability to detect false paths and handle multiple-input-transitioning...
We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of the previous RAR approaches. With the introduction of modern SAT techniques, such as efficient Boolean constraint propagation (BCP), conflict-driven learning, and flexible decision procedure, our RAR engine can identify 10x more alternative...
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