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This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm2) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives...
This paper describes the integration in a 0.13 μm CMOS of an Ultra Wide Band (UWB) receiver for communication and localization. It operates in the whole 3.2-to-4.7 GHz band of the IEEE.802.15.4a regulation mask. The proposed double quadrature coherent architecture allows exploiting high resolution capability of short pulses in the time domain, with a low sampling clock at 50 MHz. Architecture offers...
A digital radiofrequency (RF) transmitter (TX) architecture for software defined radio (SDR) is proposed in this paper. Nowadays the tendency is to integrate many telecommunication standards within a unique circuit. This leads to consider reconfigurable transmission architectures which contain a minimum of analogue components. To address the non linearity issue posed by the power amplifier (PA), an...
The work presented in this paper is the first integrated design that conciliates full digital reception, emission and baseband with low power consumption in the 4-to-5 GHz band. Power consumption is an important issue of digital reception when digitization of the RF signals into N bits needs frequencies up to 20 GHz. We hereafter describe a non-coherent receiver that simply digitizes the signal asynchronously...
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