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Motion compensation is the most critical part for the performance of H.264 decoder. Through fully analysis of the interpolation algorithm, a symmetry characteristic in the algorithm has drawn our attention. Based on a precise deduction, a new VLSI architecture for motion compensation lum interpolation is presented in this paper. This architecture is based on separated 1-D approach and reuses the horizontal...
In the design of CAVLC decoder, it is very important to reduce hardware overhead and power consumption. Since the decoding circuit of the coeff_token element costs a lot of logic resources, this paper proposed an improved decoding method of coeff_token element for H.264 CAVLC decoder. The major contribution is summarized as follows. First, a decoder module using combinational logic is developed for...
Now a number of architectures of intra frame decoder for H. 264 have been put forword, but most of them use an original decoding order. That is current block's prediction shouldn't be executed until previous block's reconstruction is finished. Obviously, this introduces much redundant time. In this paper, we proposed a 4 times 4 pipelined architecture in which current block's prediction can be paralleled...
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