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Static random access memory is usually used in the ASIC design. The performances of memory always play major role in the overall circuit. In this paper, we propose an efficient extrapolation-based timing modeling method for SRAM complier. We build the timing equation of access and cycle time of SRAM. Our proposed method only needs to simulate a small number of memory configurations with relatively...
As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters,...
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