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A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit...
We clarified the impact of the fifth material incorporation into HfSiON technology for Vth control on the reliability of high-k/metal gate stacks CMOSFETs. HfMgSiON is remarkably effective for suppressing electron traps, giving rise to a dramatic PBTI lifetime improvement for nMOSFETs. With pMOSFETs, Al incorporation is effective for the thermal deactivation of hole traps, resulting in NBTI lifetime...
Ti−Ni thin films with three different compositions (Ti−48at.%Ni, Ti−50at.%Ni and Ti−51 at.%Ni) were prepared by sputtering. The sputter-deposited films were annealed at 773 K for 1 h to achieve crystallization. The stress-strain curves for the annealed films were measured over a wide temperature range (143–473 K) using a tensile tester. All the films showed yielding followed by a plateau region in...
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