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Anomalous threshold voltage increase with area scaling of Mg- or La-incorporated high-k gate dielectrics has great impact on scaled devices. This paper reveals that much amount of Mg or La capping effects for Vt reduction was disappeared with the increase of electron mobility in narrow channel nMISFETs. This phenomenon is explained with absorption of Mg and La into STI from bulk high-k layer. The...
We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature annealing. There was...
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