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In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe...
The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown...
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