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Efficient mapping of logical processes to physical processes is one of key technologies to accelerate parallel performance simulation. Aiming at minimizing the communications between SMP nodes and between host physical processes, this paper presents a novel method named TPsmp-LP3M. It automatically extracts communication pattern of logical processes from trace and then generates a two-phase mapping...
In parallel performance simulation of parallel systems, a large amount of logic processes (LP) must be mapped to relatively small number of physical elements (PE). Previous researches have shown that different mapping schemes could result in significant variation in the whole parallel simulation cost. In this paper, we propose, implement, and evaluate a minimum communication-guided mapping (MiniCoM)...
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