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We have studied the degradation in the off-state channel surface leakage current. This shift in the device leakage was found to be driven by a hot carrier mechanism in NMOS devices. The observed subthreshold current increase was studied and its origin was determined to be charging traps. The subsequent recovery of this electrical stress induced leakage current by the application of various gate bias...
Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles...
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