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In this letter, we report for the first time the impact of gate dielectric geometry on gate tunneling in a cylindrical-gate (CG) nanowire (NW) transistor. An analytical 2-D gate tunneling model is developed and used to assess quantitatively the tunneling probability in the CG NW transistor. A reduction in gate tunneling probability is predicted in the CG NW transistor compared with a planar-gate (PG)...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
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