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This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows...
Wireless sensor networks is a key technology for new ways of interaction between computers and the physical environment. However, the energy constrained and limited computing resources of the sensor nodes present major challenges in gathering data. Since sensor nodes are densely deployed, redundant data may occur. While cluster-based data gathering is efficient at energy and bandwidth, it's difficult...
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