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This paper presents design of a new stable 14T full power efficient adder circuit. The proposed circuit is designed based on Pass Transistor Logic (PTL) network using NMOS transistor only. The proposed circuit is simulated at layout level using Microwind EDA tools for 45nm technology in terms of power and voltage level at the sum and carry nodes. The proposed circuit performance is compared with a...
In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology...
Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the delay of combinational circuits for all combination of inputs for the range of delay values based on controlling values. Hence it is possible to look up the built in library and calculate the output delay of any combinational...
This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of the proposed circuit was compared with other...
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