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Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6 T SRAM cells. To overcome this limitation, 7 T SRAM designs were proposed...
The occupancy of caches has tended to be dominated by the logic bit value `0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value `0' occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategies...
Vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high Ion/Ioff ratio (>104). At VDS = 0.75V, a record on-current of 20??A/??m is achieved due to higher tunneling rate in narrow tunnel gap In0.53Ga0.47As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming...
This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDD and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells...
Single-ended static random access memory (SE-SRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a novel six-transistor (6T) SE-SRAM bitcell for low-Vdd and high speed embedded applications with significant improvement in their power, performance and stability under process variations. The proposed design has a strong 2.65times...
Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper. Therefore, we investigate new stability metrics and report the stability analysis for typical a SRAM cell. In particular, a concept called power metric is introduced. From this metric we derive two new stability figures; static...
Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra-low voltages. Therefore, to operate cells in the subthreshold regime, new cell structures needs to be explored. Towards this, we present a single-ended I/O (SEIO) bit-line latch style 7-transistor static random access memory...
In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that...
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