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This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain...
The charge trapping characteristics of BaTiO3 film with various Zr contents were investigated based on Al/Al2O3/BaTiO3/SiO3/Si structure. The device with an appropriate Zr incorporation shows higher performance than the one without Zr doping, including higher operating speeds and better data retention. However, excessive Zr doping in BaTiO3 degrades the device performance mainly due to increased dielectric...
A self-aligned approach was developed to fabricate planar gated nanowire field emitter arrays (FEAs). A single mask was used to etch the gate dielectric and define the area for nanowire growth, in which a self-alignment between the gate and the nanowire cathode is achieved. A planar gated ZnO nanowires FEAs was fabricated by using this approach .
We demonstrate all-optical XOR logic function for 40Gb/s DPSK signals in the C-band, based on four-wave mixing (FWM) in a silicon nanowire. Error-free operation with a system penalty of ∼ 4.3dB at 10−9 BER has been achieved.
We demonstrate all-optical XOR logic function for 40Gb/s DPSK signals in the C-band, based on four-wave mixing (FWM) in a silicon nanowire. Error-free operation with a system penalty of ∼ 4.3dB at 10−9 BER has been achieved.
A systematic flow is described for characterizing, modeling, and simulating single event transient-induced soft errors in cell-based designs. Pulse broadening effects are quantified for a 65 nm CMOS process.
Scanning Kelvin probe microscopy (SKPM) is applied to experimentally understand the asymmetric behaviors in hole and electron transportation regions in graphene field-effect transistors (FETs). With gate modulation, the transition from p-p-p to p-n-p (for a Ag or Pd source/drain junction with graphene) or from n-p-n to n-n-n (for an Al source/drain junction with graphene) is verified by SKPM, which...
PIN tunneling field effect transistor (TFET) is one of the most promising devices due to its low sub-threshold swing. In this paper, using TCAD simulation, we investigate the doping and structure dependence of the electric field in PIN TFET. We show that an insertion of a thin N layer into PIN structure (i.e., PNIN TFET) not only enhances the drive current but also improves the reliability of the...
The junction contact characteristics between single layer graphene (SLG) and Ti, where Ti is prepared by various deposition processes, are investigated physically (via Raman) and electrically (via 2-point or 4-point probe measurement and residual resistance methods). For Ti deposited by electron beam evaporation (EBM) process, there are no noticeable Raman shift and weak D band in Ti junction with...
We report low Vt Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phim-eff of 5.04 and 4.24 eV, low Vt of -0.16 and 0.13 V, high mobility of 85 and 209 cm2/Vs, and small 85degC BTI les40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
For the first time, after considering the thermodynamic properties (evaluated by the molar Gibbs energy of oxide formation, DeltaOxideG) and the electronegativity (chi) for both the dopants (via ion implantation, thin capping layer or co-deposition) and host materials in the gate stack, a practical model to understand the effective work function (EWF) modulation induced by various dopants is proposed...
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