The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We study a new synchronization algorithm based on low-density parity check codes. The algorithm was developed for scenarios with redundant information in 2010, [1]. We describe a revised version of the algorithm and, for the first time, we discuss the fundamentals about the coding and decoding theory. The results of this analysis define the scope and restrictions of the algorithm. We show that the...
In this paper we propose two image watermarking algorithms, which are robust to cropping operation using self-synchronization mechanism. In both algorithms, the watermark sequence is firstly encoded by non-cyclic Low Density Parity Check Codes (LDPC) and then it is embedded into the block-wised Discrete Cosine Transform (DCT) coefficients using the Quantization Index Modulation (QIM) algorithm. In...
In this paper we propose an adaptive data hiding method that divides the host image in suitable and ineligible blocks. This classification is based on the DCT energy features from the horizontal, vertical and diagonal frequency information. Only the suitable blocks are used for data embedding using quantization index modulation (QIM). After the composite image is attacked by JPEG compression, a desynchronization...
In this paper three techniques are developed, namely: (1) a clock-data recovery (CDR)-assisted duobinary-based decision feedback equalizer (DFE) technique in which first tap feedback is eliminated, and clock phase can be accurately recovered even when using multirate clock DFE; (2) a fast dedicated-path feedback technique that achieves less than 2T feedback time for second post tap; and (3) a duobinary-based...
A 2.0 Gb/s clock-embedded interface for LCD drivers, Advanced-PPmL??, has been developed for high-speed data transfer and reduced area in transmission media. Only one pair of differential signals is needed to control the LCD driver and to display images. A newly developed 1/5-rate phase frequency detector helps achieve a 25% power reduction compared with a half-rate architecture. Pulse filtering of...
A backplane transceiver in 90 nm CMOS that employs duobinary signaling over copper traces is described. To introduce duobinary signaling into data transfers on printed boards, three techniques are developed: 1) edge equalization for equalizer adaptation; 2) 2/spl times/ oversampled transmitter equalizer for ISI control; and 3) 2b-transition-ensure encoding for clock recovery.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.