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This paper reports modeling the parasitic bipolar device in the 40 nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0 V to 2 V at the gate, the case with a slower rise time shows a faster turn-on in the...
A low supply voltage low phase noise 10-GHz CMOS quadrature LC-VCO (LC-QVCO) is systematically analyzed and designed for low power applications in wireline and wireless communication systems. Using a semi-empirical model, the impacts on VCO oscillation magnitude, loaded quality factor (Qloaded), and oscillation frequency from the parasitic components of passive and active devices are formulated in...
This paper addresses a key concern of RFIC designers: RF device models are extracted from measurements of common source (CS) devices, but are used in un-common source (UCS) RFIC designs. As well as validating RF models in a complete functional IC, we also introduce flexible active building cells, i.e. intermediate merged cascode cells (MCC) and cross couple pairs (CCP). A good match between measurements...
For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (Igb) and gate capacitance (Cgg) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12 A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence...
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