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This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of...
On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the...
Diagnosis for systematic defects is very critical for yield learning in nanometer technology. This paper presents a bridging fault diagnosis which identifies a single layer of systematic defects (LSD), where more than expected numbers of bridging faults are located. The proposed technique is a layout-aware diagnosis which contains bridging pair extraction, structural analysis, and layer-oriented covering...
The n-detection test is attractive as it achieves high defect coverage for all types of circuits and different fault models by using an easy ATPG procedure. The drawback is that it requires a much larger test set; besides, the test power is also a concern. Since the size of an n-detection test set is very large, it is possible to organize the test patterns in such a way that signal transitions are...
This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered single-capture scheme followed by the one-hot single-capture scheme for detecting structural faults, which are neither timing-dependent nor sequence-dependent in a scan design. Structural faults are also called combinational faults or DC faults, such as stuck-at faults and bridging faults. Typically,...
An automatic test pattern generation (ATPG) technique, which simultaneously reduces capture and shift power during scan testing, is presented. This ATPG performs power reduction during dynamic test compaction so the test length overhead is very small. This low-power test generator implements several novel techniques, such as parity backtrace, confined propagation, dynamic controllability and post-fill...
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