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FinFET devices are extensively investigated due to the prospects for application in the sub-100 nm CMOS integrated circuits fabrication. Small size of the FinFETs and the properties of technological processes strongly influence their electrical characteristics. The random variations of the characteristics lead to a mismatch effect critical from the viewpoint of design and fabrication. In the paper...
Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure, composition and powering on the FinFET topography. Next, the most important geometric parameters of the FinFETs have been varied and the electrical characteristics...
A methodology of FinFETs characterization based on electrical characteristics of FinFET devices have has been proposed. The measured channel and gate current vs voltage characteristics of sets of devices with different fin width have been used for evaluation of the FinFETs parameters. Namely, a channel current data have been used for estimation of threshold voltage, transconductance coefficient, effective...
A test 3-Gate FinFET-type p-MOS transistor was manufactured using a 3um CMOS layout and a technique dedicated for preparation of 270nm narrow silicon paths, controlled by means of a lateral definition process (PADEOX). SEM and optical views of the device were presented. I D (V DS) and I D (V GS) characteristics were measured and displayed together with typical p-MOS curves. A simple model of I-V characteristics...
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