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We present an overview of research on integrated diode circuits for terahertz applications carried out at Chalmers University of Technology. This includes progress on heterogeneous integration of heterostructure barrier varactor multipliers on silicon substrates. The described technology uses silicon-on-insulator (SOI) substrates, for which accurate and well-defined substrate thickness for the microstrip...
A depth image provides geometric information of a 3D scene, namely the shapes of physical objects captured from a particular viewpoint. This information is important for synthesizing images corresponding to different virtual camera viewpoints via depth-image-based rendering (DIBR). Since it has been shown that blurring of object contours in the depth images leads to bleeding artefacts in virtual images...
We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS ultra low leakage of <2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.
The 140 GHz silicon micromachined bandpass rectangular waveguide filters are firstly fabricated by the deep reactive ion etching (DRIE) processes for submillimeter wave applications. The filter circuit structure is once-formed using the ICP reactive ion etcher to etch through the full thickness of the silicon wafer, and then bonded together with the two metallized glass covers to form the waveguide...
In this work, the composition distribution in SiC films grown on Si(111) using chemical vapor deposition (CVD) method has been measured by the plan-view energy dispersive spectroscopy (EDS). The measuring original EDS data are modified by considering the multilayer structure and the attenuation due to the diffuse reflection at the interface of the voids. The relative error rate of the improved EDS...
A new universal stress retardation parameter set is successful to account for initial oxidation rate enhancement, orientation-dependent retardation and self-limiting phenomena observed in the dry oxidation experiment of the silicon FIN nanostructures over a wide temperature range. This stress-retarded orientation-dependent model was proved to be trustworthy in shape engineering of silicon nanowire...
In this work the charge-based capacitance measurement (CBCM) method has been extended and calibrated to measure sub-fF level bias-dependent capacitance of single channel silicon nanowire (SNW) transistors. Mixed mode simulations are used to establish the efficacy of the method. Test keys have been carefully designed and fabricated on-chip so that C-V and I-V characteristics are measured on the same...
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs...
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
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