The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper reports a single-chip full-band 3.1 10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18μm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak...
A 3.1-4.8GHz two-stage LNA for Group-1 UWB applications featuring current reuse, resistive feedback, complete and high ESD protection design is reported. ESD-RFIC co-design technique was used to ensure whole-chip optimization. The design is implemented in a foundry 0.18μm RFCMOS. Measurement shows a gain of 13.2dB/14.0dB, excellent input reflection of -13.4dB/-17.5dB, noise figure (NF) of 5.11dB/4...
A 3.1-4.8GHz LNA for lower-band UWB transceiver front-end ICs designed in a commercial 0.18μm CMOS is presented. The LNA features current reuse, resistive feedback, complete and robust full-chip ESD protection. LNA circuits with and without ESD protection are compared to minimize ESD-induced LNA performance degradation. Experiment shows a gain of 13.2dB, excellent input reflection of -13.4dB, NF of...
This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.