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Adequate ESD protection is a new design challenge for HV electronics. This paper presents design, failure analysis and optimization of a HVggLDMOS ESD protection structure in a HV BCD process. Theoretical analysis involving Kirk effect and mixed-mode ESD simulation-design technique were used to analyze experimental results and to optimize the HV ESD protection structure.
We demonstrate key factors enabling mobility improvement at both low charge density and high density (>5 × 1012/cm2) in In0.7Ga0.3As quantum-well MOSFETs. We further show sub-threshold swing (SS) and on-current (Id) improvement in tunneling FETs (TFETs). By reducing EOT, optimizing the top-barrier/high-κ interface, and confining carriers in In0.7Ga0.3As channel using In0.52Al0.48As bottom-barrier,...
Deep-submicron In0.7Ga0.3As buried-channel MOSFETs with various gate lengths down to 40 nm are demonstrated. In0.7Ga0.3As buried-channel MOSFETs were fabricated on an epitaxial wafer using an InP/In0.52Al0.48As double barrier. The device characteristics were analysed, including subthreshold swing, transconductance and drive current. Good scaling behaviour was observed for these III-V MOSFETs. For...
The performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is a key to reduce border traps, interface traps and move ZrO2 fixed charge away from the In0.53Ga0.47As. Border traps are reduced ~3x, effective fixed charges are reduced ~3x and...
This paper compares device performance for In0.53Ga0.47As MOSFETs using single HfO2 gate dielectric with stacked gate dielectrics using various interfacial layers between HfO2 and In0.53Ga0.47As substrate including Al2O3, HfAlOx, LaAlOx, and LaHfOx. Of the gate stacks studied, Al2O3/HfO2, HfAlOx/HfO2, and LaAlOx/HfO2 bilayer gate dielectrics exhibit lower subthreshold swing, higher drive current and...
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs...
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
Using a thin germanium interfacial passivation layer (IPL), for the first time we present surface channel n- and p-MOSFETs on GaAs substrate with TaN gate electrodes and HfO2 dielectric films. We used self-aligned and gate-last processes to fabricate MOSFETs on semi-insulating GaAs substrate. The electrical results from the buried channel and the surface channel-mode transistors are investigated....
In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not always result in a straightforward performance...
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