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In this paper we demonstrate a solution to achieve robust enhancement-mode Al2O3/GaN MISFETs with a high breakdown voltage and suggest a possible model for the device off-state breakdown. It is found that the device breakdown exhibits different gate voltage dependence for different surface treatments before the gate dielectric deposition. The device performance is greatly improved by using an in-situ...
This paper investigates the physics of device failure during avalanche for 1.2 kV SiC MOSFETs, silicon MOSFETs and silicon IGBTs. The impact of ambient temperature, initial conditions of the device prior to avalanche breakdown and the avalanche duration is explored for the different technologies. Two types of tests were conducted namely (i) constant avalanche duration with different peak avalanche...
Using the Fourier series solution to the ambipolar diffusion equation, the robustness of the body diodes of SiC MOSFETs during reverse recovery has been studied. Parasitic bipolar latch-up during the reverse recovery of the body diode is a possible if there is sufficient base current and voltage drop across the body resistance to forward bias the parasitic BJT. SiC MOSFETs have very low carrier lifetime...
An ultra-low power pipelined ADC is realized by replacing conventional op-amp circuits with dynamic source-follower gain stages. The presented 90-nm CMOS converter operates at 50 MS/s and achieves an SNDR of 49.4 dB while dissipating 1.44 mW from a 1.2-V supply.
A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complimented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time...
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