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Min timing violations are fatal and need to be fixed in order to avoid chip failure. HoldAdvisor is used in chip design to find good locations for buffer insertion or swaps to assist in min timing fixing. Previously published work on buffer insertion has mainly focused on reducing delays to fix max timing violations. Those approaches cannot be directly applied to delay insertion for fixing min timing...
A neural based PID feedback control method for networked process control systems is presented. As there are some uncertain factors such as external disturbance, randomly delayed measurements or control demands in real networked process control systems, the proposed PID controller is implemented by backpropagation neural networks whose weights are updated via minimizing tracking error entropy of closed...
According to the theory of constraints (TOC), bottleneck should be made full use while non-bottleneck should be subordinate to the bottleneck. However, for the multi-bottleneck permutation flow-shop scheduling problem (PFSP), different bottleneck causes different driving force resulting in different even conflicted scheduling solution. Aiming at this problem, the multi-objective mathematical model...
The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable single-core system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate how the data-learning approach can be applied to predict multi-core system Fmax,...
The question of whether or not structural test measurements can be used to predict functional or system Fmax, has been studied for many years. This paper presents a data learning approach to study the question. Given Fmax values and structural delay measurements on a set of sample chips, we propose a method called conformity check whose goal is to select a subset of conformal samples such that a more...
This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise...
We present the design and development of an amplitude compensated long time delay circuit (LTD) in multilayer liquid crystal polymer (LCP) films. The design is implemented with MEMS switches. An LTD is built on a thin-film multilayer stack to provide a variety of transmission lines to offer different attenuation characteristics for amplitude compensation. True time delay (TTD) components produce 0...
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