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The performance of in-memory based data analytic frameworks such as Spark is significantly affected by how data is partitioned. This is because the partitioning effectively determines task granularity and parallelism. Moreover, different phases of a workload execution can have different optimal partitions. However, in the current implementations, the tuning knobs controlling the partitioning are either...
Nview Multidisplay technology is getting popular in many fields. In order to allow a high degree of parallel processing, the processing units would be massively replicated on the chip. Traditional bus based architecture faces scalability issue. In this paper, we introduce the concept of network on chip to Nview Multidisplay application. The 2D Mesh topology is explored based on the requirement of...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of the transformation towards 4G. In this paper, we describe an energy efficient multi-Gbps LDPC decoder engine based on ASIP using Target tool suite. The ASIP core can be configured as half-layer paralleled or quarter-layer paralleled decoding, which offers a good trade-off between the throughput and power/area...
MapReduce programming model is widely used for large scale and one-time data-intensive distributed computing, but lacks flexibility and efficiency of processing small incremental data. IncMR framework is proposed in this paper for incrementally processing new data of a large data set, which takes state as implicit input and combines it with new data. Map tasks are created according to new splits instead...
Today's information is increasing rapidly, doubling every three years. Consequently, the search and recognition stages in computer applications will consume a growing portion of the total CPU time. The SSE 4.2 instruction set, first implemented in Intel's Core i7, provides string and text processing instructions (STTNI) that utilize SIMD operations for processing character data. Though originally...
General Purpose computing on Graphical Processing Units (GPGPU) is a paradigm shift in computing that promises a dramatic increase in performance. But GPGPU also brings an unprecedented level of complexity in algorithmic design and software development. In this paper, we present an efficient parallel fault simulator, FSimGP2, that exploits the high degree of parallelism supported by a state-of-the-art...
Lattice reduction is a promising technique to enhance the performance of sub-optimal MIMO detectors. This paper presents the Bounded Block Parallel Lattice Reduction (BBP-LR) algorithm, which is an implementation friendly low complexity algorithm specifically optimized for practical MIMO-OFDM systems. The optimisation of the BBP-LR algorithm is based on the following: 1) exploiting the frequency coherence...
In this paper parallel program was performed for the FDTD electromagnetic algorithm on a multi-core CPU computer with CUDA device. In the case of two-dimension FDTD method, computation times were measured and compared to investigate the efficiency of parallel FDTD application. The results show that CUDA parallel program can improve the computing performance efficiently which can be used for three-dimension...
ML and near-ML MIMO detectors have attracted a lot of interest in recent years. However, almost all of the reported implementations are delivered in ASIC or FPGA. Our contribution is to co-optimize the near-ML MIMO detector algorithm and implementation for parallel programmable base-band architectures, such as DSPs with VLIW, SIMD or vector processing features. Although for hardware the architecture...
A good concurrency control method that maximizes the operational parallelism while prevents conflicts of simultaneous manipulations is vital for cooperative design systems and still a challenge. We propose an adaptive granular concurrency control approach for the replicated collaborative feature modeling based on the feature dependency directed acyclic graph (FDAG). According to the varying design...
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