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TSV (Through-silicon Via) meets the demands of high speed and low power consumption in 3D integrated circuits. However it faces challenge in signal integrity problem such as crosstalk. TSV to TSV coupling is the most significant crosstalk problem in TSV based 3D ICs. This paper presents a quantitative estimation on the TSV to TSV crosstalk induced interconnect delay, trying to find the worst interconnect...
In this paper, TSV noise coupling is investigated in terms of both noise transfer function and signal integrity. An electrical model of coupled TSVs is presented and verified by 3-D field solver. Additionally, influence on TSV noise coupling transfer function with different TSV height, pitch and the thickness of insulation layer is analyzed. The electrical model helps to simplify the analyzing process...
Testing for three dimensional (3D) integrated circuits (ICs) based on through-silicon-via (TSV) is one of the major challenges for improving the system yield and reducing the overall cost. The lack of pads on most tiers and the mechanical vulnerability of tiers after wafer thinning make it difficult to perform 3D Known-Good-Die (KGD) test with the existing 2D IC probing methods. This paper presents...
As technology scales, modern massive parallel processing (MPP) systems are facing large system overhead caused by high failure rates. To provide the system-level fault tolerance, the traditional in-disk checkpointing/restart schemes are usually adopted by periodically dumping system states and memory contents to hard disk drives (HDDs). When errors occur, the system can be restored by reading checkpoints...
Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the “memory wall” challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint...
In recent 3DIC studies, through silicon vias (TSV) are usually employed as the vertical interconnects in the 3D stack. Despite its benefit of short latency and low power, forming TSVs adds additional complexities to the fabrication process. Recently, inductive/capactive-coupling links are proposed to replace TSVs in 3D stacking because the fabrication complexities of them are lower. Although state-of-the-art...
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