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Channel Hot Carrier (CHC) and Negative Bias Temperature Instability (NBTI) degradation has been studied in pMOSFETs with and without channel strain. The results show larger CHC degradation and a neglegible influence of NBTI on strained pMOS devices. The degradation effects are modeled to be introduced in a circuit simulator. The simulations of a CMOS inverter, which has been chosen as example circuit,...
The reversibility of the gate dielectric breakdown (DB) in ultrathin high-k dielectric stacks is reported and analyzed. The electrical performance of MOSFETs after the dielectric recovery is modeled and introduced in a circuit simulator. The simulation of several digital circuits shows that their functionality can be restored after the DB recovery.
To clarify the impact of the gate oxide degradation and breakdown (BD) on CMOS circuits functionality it is necessary to develop models for broken down devices that can be included in circuit simulators. Transistors with different geometries have been experimentally stressed to provoke oxide degradation and BD. The transistors characteristic curves after degradation have been fitted with SPICE BSIM4...
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