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With rapid technology scaling, the proportion of the static power catches up with dynamic power gradually. To decrease leakage power is becoming more and more important in low-power design. Base on the pact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, p-type complementary pass-transistor logic (P-CPL) and p-type differential cascade voltage switch logic (P-DCVSL)...
In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce the leakage power is dual-threshold techniques. Low-threshold transistors are assigned to critical paths of the circuits to enhance the performance, while high-threshold transistors are assigned to non-critical paths to reduce the leakage current. This paper proposes a...
A 32times32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18 mum process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show...
In present CMOS circuits, the scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to both leakage dissipations and total power consumptions. This paper proposes a new flip-flop, which uses P-type CMOS technique, power-gating and dual threshold technique to reduce both sub-threshold and gate leakage...
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