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This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly...
Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge...
Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulator structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related...
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