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Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (D it ) of SiGe/BOX are...
Defects generated during the temperature ramping process were evaluated by photoluminescence (PL) for Si/SiGe/Si-on-insulator structure, which is the typical structure for SiGe-on-insulator (SGOI) virtual substrate fabrication using the Ge condensation by dry oxidation. The free exciton peaks were clearly observed for the as grown wafers and decreased with the increase of annealing temperature. Defect-related...
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