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An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the...
A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also save power compared with the conventional designs. A source-series terminated (SST) driver with a 2-tap feed-forward equalizer (FFE)...
A source-synchronous serial link receiver with an adaptive quarter-rate 2-tap DFE and a baud-rate CDR is demonstrated. The data-sampler-lane (DSL) of the DFE uses the combination of the soft-decision technique and a new dynamic structure to achieve a power efficiency of 0.24mW/Gb/s. The error-sampler-lane (ESL) based on the same dynamic structure is shared by the DFE adaption logic and baud-rate CDR...
This paper presents a fast mixed-signal automatic gain control (AGC) method for zero-IF/sliding-IF receivers used in wireless personal and body-area networks (WPAN/BAN). The preamble defined in Bluetooth low energy (BLE)/802.15.4 /802.15.6 specifications are as low as 1 Byte. It is a tough challenge for the zero-IF/sliding-IF receivers to perform AGC training, frequency synchronization and symbol...
A UHF RFID reader receiver is implemented in 0.18μm CMOS. The direct-conversion receiver consists of an LNA, passive mixers, baseband PGAs and LPFs. As high as 18.5dBm measured IIP3 of the RF front-end is achieved by using passive mixers driven by 25% duty cycle square wave LO. The receiver has a sensitivity of -77dBm in the normal mode and -87dBm in the LBT mode. The total power dissipation in the...
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