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New tendencies envisage multi-core as a promising solution for embedded application. And the key challenge is how to improve the communication efficiency. In this paper, we propose improved on-chip communication architecture for multi-core embedded system The presented on-chip communication protocol is based on packet connected circuit (PCC), but we improve it to fit different frequency requirements...
Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for multi-core System on Chip, of which there are three kind of components, processing element(processor, memory, IP, etc), communication element(such as router) and interface module between router and PE. One of the key problems is how to solve the memory bottleneck under the circumstances that multiple...
Universal bus interface is very helpful for improving the popularity of the device or equipment on both SoC integration and board level computing system design. Because of the diversity of bus interface accessing protocol, universality is usually unable to be achieved in a common interface design. Through introducing the concept of sequence configuration, a method of designing universal bus interface...
While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed...
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