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This paper presents a 40Gbps SerDes transceiver consuming only 190mW power. The transmitter employs serializing time window search technique and 2-tap pre-emphasis. The receiver implements power-efficient front-end circuits including current-integrating FFE and cascaded dynamic comparators. The CDR employs a bang-bang phase detector, and the integral path and proportional path are separated. Fabricated...
This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically...
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