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Blum-Blum-Shub (x2 mod N) is proved cryptographically secure pseudorandom generator which passes all the statistical properties of randomness tests. It is secure, because it cannot predict in forward direction as well as in backward direction. The reason is hard to factorize the large integer N (≥ 264) which is the product of two special primes. The major challenge of BBS is the efficient...
In this paper, the design methodology and implementation of a digitally controlled, synchronous gate driven and flexible Electronic Power Conditioner (EPC) have been discussed. With incorporation of an FPGA (Field Programmable Gate Array) as its controller, forward topology with active clamp Zero Voltage Switching (ZVS) Technique and synchronous rectification, this dc-dc converter offers flexibility...
The main aim of this paper is to design a parameterized 32 bit floating point multiplier which is based on IEEE 754-2008 binary interchange format. The proposed work is capable of checking overflow and underflow using corresponding flags by flagger circuit. In this design rounding modes are also considered based on the two bit control signal provided as input such as round to nearest even, round to...
The variety of applications for field programmable gate arrays (FPGAs) is continuously growing, thus it is important to address power consumption issues during the operation. As technological node shrinks, leakage power becomes increasingly critical in overall power consumption of FPGA. The technique of configuration pre-fetching (loads configurations as soon as possible) adopted to achieve high performance...
Nelder-Mead algorithm (NMA) is the best-known algorithm for multidimensional optimization without involving derivative computations. Due to the simplicity in implementation and the fast convergent property of NMA, it is widely used in the fields of statistics, engineering, physics and medical sciences. In practice, when objective function is complicated, the optimization procedure requires a lot of...
These days, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer (RISC) core, and many operations--such as discrete cosine transform (DCT), inverse DCT, discrete Fourier transform (DFT), and fast Fourier transform (FFT)--are performed by a digital signal processor (DSP) system. Here, the authors present the design of a RISC and DSP system that uses very high-density...
LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for getting better efficient result. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design...
In this paper we have designed and implemented (15, k) a BCH Encoder on FPGA using VHDL for reliable data transfer in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organised into shift register circuits. Using the cyclic...
The main purpose of this paper is to study the FPGA implementation of two 16 bit PN sequence generator namely Linear Feedback Shift Register (LFSR) and Blum-Blum-Shub (BBS). We have used FPGA to explain how FPGA's ease the hardware implementation part of communication systems. The logic of PN Sequence Generator presented here can be changed any time by changing the seed in LFSR or by changing the...
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