The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As the size of MOS transistors are scaling down, energy dissipation has become a major consideration in nanometer CMOS circuits. In this paper, a Full-Adder is realized using XOR gate in sub-threshold region and the results shows that the device works perfectly without affecting its functionality keeping the power, delay and power-delay product at an optimum level. The analysis is done in Cadence...
The basic arithmetic operation used in many VLSI circuits is addition, therefore reduction in power dissipation of 1-bit adder cell will improve the performance of most of electronic devices. Carbon nanotube field effect transistor (CNTFET) is found to be one of the most promising alternatives for MOSFET. The CNTFET is a transistor in which a carbon nanotube (CNT) is used in the channel region. In...
This paper puts forward a comparison between two 1 bit full adder designs: one using 4T XOR and the other using 4:1 MUX based 3 Input XOR. Both are designs are made up of 10 transistors. The simulation is done using Cadence Simulator at 180nm and 90nm Technology. Comparison is made among the two proposed designs with respect to power and delay. The results show the efficiency of the design.
This paper puts forward digital circuit design using Binary Decision Diagram (BDD). BDDs can be implemented using 2:1 mux. In this paper 2T and 4T mux are used to for digital circuit design. The BDD simulation is done using CUDD-2.5.0 tool and mux implementation is done using DSCH 2.7f and Microwind 2.6k Simulator. Experiments are performed on ISCAS Benchmark Circuits at 90 nm technology. The results...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.