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This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated...
A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3–7V.
This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BVds-Rsp, gm, HCI reliability, and forward safe operating area figures-of-merit. The planar dual...
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