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A 10–20 Gb/s clock and data recovery (CDR) circuit with frequency tracking is presented. Two digital phase interpolators (PIs) are used to track the frequency of input data. The loop bandwidth of the CDR circuit is adaptively adjusted. A mixed-mode PI is used to generate the recovered clock. This CDR circuit is fabricated in a 40nm CMOS process and its area is 0.33×1.0 mm2. Its power consumption is...
A digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration is presented. The proposed bandwidth calibration circuit adjusts the proportional and integral gain of the digital loop filter to tolerate the process, voltage and temperature (PVT) variations. This BBPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0049 mm2 and the power is 3.34 mW from a supply of 1.1 V. The...
A 5–20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10...
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