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This paper presents design and verification of a 10Gbps in-line Network Security Processor (NSP) with a single 32-bit embedded CPU. This NSP is designed to process the IPSec protocol at line speed for the 10Gbps Ethernet. 10Gbps SerDes, IPSec protocol processing module, database query module, and a CPU are designed to be integrated on one chip to form a System on Chip (SOC). The CPU used is OR1200,...
10Gbps Ethernet Security Processor is very important in future network telecommunication. In order to meet the performance of ultra high throughput of 10Gbps ESP, An architecture of multiple SHA-1 IP cores paralleled based crossbar switch are proposed in this paper. Firstly, An ultra high throughput, low power consumption SHA-1 algorithm IP-core are designed, then, an effective scheduling architecture...
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