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This article presents the design of a driver system for vertical cavity surface emitting lasers (VCSELs), including limiting amplifier, delay circuit, driver circuit and 5-bits DAC. By adding a delayed pulse on the original data signal, the VCSEL driver adopts a new method to compensate the ringing generated by the bound-wire inductance, pad capacitance and VCSEL. Through adjusting the delay time,...
This paper presents a power efficient static frequency divider (SFD) for wideband operation. Series inductive peaking technique is utilized to construct broadband input network of the divider. The aspects of design using the technique are supported with exhaustive simulations. The prototyped divided-by-two frequency divider is implemented in 65 nm LP CMOS technology. Measurement results show that...
A 6.25Gb/s 3-tap T/2-spaced feed-forward equaliser (FFE) is realized in 0.18μm CMOS Technology. The proposed FFE can be used to reduce the inter-symbol interference (ISI). A high frequency boost delay element using source capacitive degeneration is adopted to meet the high speed requirement. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations...
This paper presents a 1.25Gb/s high gain optical receiver pre-amplifier featuring a wide dynamic range in 0.35µm standard CMOS. The designed amplifier is configured on three identical stages, incorporating the automatic gain control (AGC) technique to achieve a wide input dynamic range and a good noise performance. The post-simulations demonstrate the transimpedance gain of 80.5dBΩ, the −3dB bandwidth...
In this letter, a 2 × 2 thermo-optic waveguide-based switch with ultralow power consumption is demonstrated and fabricated using a standard complementary metal-oxide-semi conductor (CMOS) process. The phase arms are suspended by removing adjacent SiO2 and 120 μm of the underlying Si, while leaving a few SiO2 beams to support the suspended phase arms for the purpose of structural strength. As compared...
To reduce the power consumption, a 4:1 multiplexer using the CMOS logic is presented for high-speed operation. The proposed circuit adopts tree-type and half-rate structure. The CMOS logic, such as the dynamic CMOS and pseudo-static CMOS logic, is renewed in this design. The designed circuit is realized in a standard 0.18 μm CMOS process and uses 1.8 V supply voltage. The post simulated result shows...
A tree-type 4:1 multiplexer (MUX) is designed by employing CMOS logic and eliminating impedance matching of the signal ports. The proposed circuit is realized in a 0.35-μm CMOS process. With the whole power consumption of 60 mW from a 3.3 V supply voltage, the MUX can operate at an output rate up to 3.6 Gb/s. From the measured eye-diagrams, the MUX exhibits an output voltage swing of 250 mVpp with...
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