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This paper proposes an area-efficient Viterbi decoder architecture for digital radio receivers, which exploits the new features offered by modern FPGA. Implementation results show that our architecture meets the throughput requirements for the DAB and DRM standards, while consuming extremely few hardware resources
This paper deals with the development of reusable FFT cores for OFDM in the light of the new features offered by modern FPGAs and synthesis tools. A pipelined and a sequential architecture have been selected as case studies to show how the requirements of various OFDM standards affect the choice of the optimal FFT architecture
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