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We present a novel fully-depleted SOI CMOS technology with dielectrically-isolated polysilicon back gates, achieved by a double BOX substrate combined with dual-depth shallow trench isolation. CMOS devices down to 30nm gate length are fabricated with high-κ/metal gates. A novel isolation structure with liners is shown to achieve robust isolation between devices and back gates. Effective back gate...
In this work we present a potential solution for forming ultra-shallow junctions with extremely low contact resistivities in which dopants are implanted into silicides and diffused to the semiconductor interface using low temperature anneals. Conventional silicide process requires a fine tuning of silicide thickness and deep source/drain doping profile to achieve low contact resistance and low source/drain...
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed...
Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell,...
Context awareness is one of the most fundamental issues in pervasive computing. In this paper, component based context model based on middleware architecture is proposed. Moreover, OWL-based context ontology for modelling context information to easily share and reuse context knowledge is presented. By giving fire alarm scenario for our prototype, the proposed component based context architecture can...
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