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This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm2 design. This corresponds to ~30 M estimates per second, which is...
This paper presents a low-complexity DDS IC for subcarrier processing in an FM-UWB transceiver. The IC implements data pre-filtering and FSK generation for the transmitter and quadrature LO signals generation for the receiver. The use of DDS techniques yields accurate signals whose parameters can be easily adjusted to accommodate a wide range of sub-carrier frequencies and bit rates. An interpolating...
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