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Due to the charge at the interfaces between the silicon substrate and its outer region, the admittance of the through silicon vias (TSVs) near the edge and at the corner of the silicon is different from that of the centre case, which is hardly calculated by conventional empirical formulas. Utilising the method of moment combined with the image method in this study, those admittances can be easily...
Thermal issue is a leading design constraint for three-dimensional integrated circuits (3D-ICs) and through silicon vias (TSVs) are used to reduce the temperature of 3D-ICs effectively. In this paper, the finite difference method-based heat conduction equations is proposed for the thermal analysis of the TSV structures in 3D-ICs and generalized minimum residual method (GMRES) with symmetric successive...
This paper presents a methodology to characterize the electrical behaviors of mixed conventional and coaxial through silicon vias (TSVs) network in three-dimensional (3-D) integrated circuits. An equivalent circuit model is established to predict the insertion loss and crosstalk level of the mixed TSV network. By the proposed model, the shielding effectiveness of the outer conductor in coaxial TSV...
This paper proposed a novel modeling of the TSV MOS capacitance by finite difference (FD) method without the assumption of the full depletion approximation (FDA). The potential distribution in the oxide liner and depletion region can be obtained by FD with only one iteration. With the potential distribution, the TSV capacitance-voltage (C-V) characteristics can be easily obtained and good agreements...
This paper proposed a novel modeling of the TSV MOS capacitance by finite difference (FD) method without the assumption of the full depletion approximation (FDA). The potential distribution in the oxide liner and depletion region can be obtained by FD with only one iteration. With the potential distribution, the TSV capacitance-voltage (C-V) characteristics can be easily obtained and good agreements...
An equivalent circuit model for low pitch-to-diameter ratio (P/D) through silicon via (TSV) in three-dimensional integrated circuit (3-D IC) is proposed in this paper. The shunt admittance of this model is calculated based on the method of moments which can accurately capture the proximity effect for both a TSV pair and TSV array. The metal-oxide-semiconductor (MOS) capacitance of TSV is also considered...
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