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A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection. For inter-symbol interference (ISI) cancellation, half-rate decision-feedback equalizer (DFE) with unrolled first tap is widely used to avoid noise amplification...
A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on...
CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases of I/O VDD to core VDD latch-up and...
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