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In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial...
Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is...
We present a self-repairing SRAM to reduce parametric failures using an on-chip leakage sensor and application of proper body bias. Simulations in a predictive 70nm technology show 5-40% (depending on inter-die Vt variation) improvement in SRAM yield. A test-chip is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the self-repair system
In nanoscale technology, large variations in process parameters produce wide delay spread in high performance circuit. In this paper the authors developed analytical models for yield prediction with respect to delay variation of pipeline design. The converse problem of estimating the design space for individual pipe stages based on a target yield has been addressed. For an example 4 stage pipelined...
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