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The authors describe an experimental 128k CMOS ECL-(emitter-coupled-logic)-compatible static RAM which has pipelined architecture and circuit techniques providing 6.5-ns first access and 5-ns cycle operation for fully random read/write. Using an all-CMOS technology, this cycle, combined with the 32-bit data I/O (input/output) capability, offers data bandwidth as high as 6.46 Gb/s. The technology is...
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