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This paper describes a new delay locked loop (DLL) architecture with infinite-skew tracking range. This is accomplished by two inverse operating delay lines, which work in a ping-pong fashion. Only a small number of delay elements are required, leading to a low delay gain and resulting in improved jitter performance compared to state of-the-art DLLs. The architecture has simple control, inherent start-up...
This paper presents a 6x OSR receiver for 200M-2Gb/s, comprising an adaptive equalizer that is auto-calibrating on sample data statistics. This robust and highly digitized receiver is demonstrated in 0.18mum CMOS and can equalize variable cable losses up to 22dB. The self-adaptive equalizer solution occupies only 0.08mm2 and consumes 9-16mW
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