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Despite being originally inspired by the central nervous system, artificial neural networks have diverged from their biological archetypes as they have been remodeled to fit, particular tasks. In this paper, we review several possibilites to reverse map these architectures to biologically more realistic spiking networks with the aim of emulating them on fast, low-power neuromorphic hardware. Since...
In this paper we describe our approach towards highly configurable neuromorphic hardware systems that serve as useful and flexible tools in modeling neuroscience. We utilize a mixed-signal VLSI model that implements a massively accelerated network of spiking neurons, and we describe a novel methodological framework that allows to exploit both the speed and the programmability of this device for the...
We will set up a fully functional system consisting of a custom design hardware framework (Figures 1 and 2) with the neural network chips described in the appended 4-page paper, Section II-A. The framework is connected digitally to a host PC, on which we will run a software that provides the simulator-like, flexible and non-expert usability of the neuromorphic device as described in the appended paper,...
Under typical synaptical stimulation, cortical neurons exhibit a total membrane conductance which, compared to a situation without any input spikes, is significantly increased. This results in a shorter membrane time constant and thus in an increased capability of the neuron to detect coincidences in its synaptic input. For this study, a neuromorphic hardware device was utilized, which does not provide...
An analog VLSI hardware architecture for the distributed simulation of large-scale spiking neural networks has been developed. Several hundred integrated computing nodes, each hosting up to 512 neurons, will be interconnected and operated on un-cut silicon wafers. The electro-technical aspects and the details of the hardware implementation are covered in a separate contribution to this conference...
Hardware compilation flows use a high-level language like C++ or Java and translate it directly to an HDL. In this paper we propose to split the problem in two; first use a regular compiler to do the front-end processing, then use the generated machine code to produce the HDL. The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. M2V...
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