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In this study, the creep-fatigue behaviors of the Sn-4Ag/Cu solder joints were investigated using in-situ tensile stage. The results reveal that the creep-fatigue process is composed by the strain hardening stage, steady deforming stage and accelerating fracture stage. During the initial few cycles, the strain increases rapidly because the solder is soft. After the strain hardening becomes saturated,...
The fatigue fracture behaviors of a series of Cu/lead-free solder joints deformed under different directions of loadings were investigated in this study. Observation results showed that fatigue cracks generally initiate around the IMC/solder interface when the loading axis is vertical to the interface. For all the solder joints, the interfacial deformations are resulting from strain localization induced...
The current study revealed that the growth kinetics and the interfacial reaction of the Cu/Sn/Ag couples with different thickness solder. For the Cu/Sn/Ag couples, plate-type Ag3Sn was firstly formed at the Sn/Cu interface rather than at the Sn/Ag interface for the Cu/Sn/Ag couple at the initial state of the reflow procedure when the solder thicknesses is 150 μm or 300 μm. Besides, the microstructure...
The bimodality of upstream electromigration (EM) failures in the dual damascene structure of 45 nm Cu interconnection process with low-k material is investigated, and the improvement is demonstrated. Two major early failure modes with voids forming in via or at the chamfer of via-trench transition area are revealed and attributed to liner process weakness at the respective locations, which can be...
The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45 nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA)...
The drive for greater integrated circuit performance has led to the need for faster interconnect systems and the development of porous ultra low k dielectrics. The porous structure and lower modulus has made integration a greater challenge. Nanoglass/sup TM/ E is one such spin-on dielectric that has been optimized for this challenge. In this study, Nanoglass/sup TM/ E dielectric copper single level...
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