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This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature...
In today's system-on-chip (SOC) design process heterogeneous technology cores are integrated at several layers of hierarchy. Hence, multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical SOCs that contain earlier generation SOCs as embedded megacores. Unlike previous works that mostly assumes flat test hierarchy, the proposed technique considers the design...
Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC...
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