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This paper addresses the problem of application mapping for Mesh-of-Tree (MoT) based Network-on-Chip. It proposes a new algorithm based on Kernighan-Lin partitioning to identify closely related cores of the application. The nodes are then mapped to the topology using another heuristic algorithm. The MoT mapping results have been compared with the mesh-mapping results reported in the literature for...
This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature...
This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.
This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement...
This paper present a new dimension-oriented routing algorithm for Mesh-of-tree (MoT) based Network-on-Chip (NoC) architecture. The addressing scheme is considerably simplified that enables us to reduce the minimum flit-size to 16-bits, compared to 32-bits in the previously reported works. The same level of throughput and average latency could be achieved with a 43.86% reduction in area and 43% reduction...
The actual traffic data collected on various applications specific on-chip networks exposed that the network traffic is self-similar in nature. In this work, modeling of self-similar traffic by aggregation of a large number of on-off Pareto sources has been discussed. We have developed a cycle accurate network simulator for evaluating the performance of wormhole router based network by varying locality...
Scalability has become an important consideration in Network-on-Chip (NoC) designs. The word scalability has been widely used in the parallel processing community. For massively parallel computing, a scalable system has the property that performance will increase linearly with the system size. The scalability analysis may be used to select the best architecture for a problem under different constraints...
Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. NoC has emerged as a new paradigm for designing core based System-on-Chip (SoC). The success of NoC design relies...
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